Pooya Ronagh

The key factor in determining the speed of a fault-tolerant quantum computer is the reaction time of its classical electronics, that is, the total time required by controllers and decoders to determine the outcome of a logical measurement and refactor this information in the subsequent logical operations conditioned on the measurement outcome. We first show how the logical microarchitecture of a quantum computer based on the surface code can be optimized with respect to the reaction time. Then, using parallel space- and time-window decoding methods, we build a model for decoder latency, which we use to estimate the increase in the logical error rate of magic state injections as a function of the reaction time. Finally, we present detailed resource estimates for executing utility-scale quantum circuits based on realistic hardware noise parameters, state-of-the-art decoding times, and our envisioned quantum execution environment comprising a high-speed network of QPUs, controllers, decoders, and HPC nodes.